The invention relates to an input buffer circuitry of an LSI, directly receiving a signal inputted from outside.
The input-output characteristic of CMOS inverters making up an input buffer circuitry indicates how an output voltage varies against an input voltage based on a ratio of xcex2 an N type MOS transistor to that of a P type MOS transistor, that is, a xcex2 ratio xcex2=xcex2N/xcex2P={W (gate width)/L (gate length)}N/(W/L)P as a parameter. Herein, a MOS transistor refers to a MOS type transistor such as a MOSFET, and so forth.
Referring to FIG. 8, a case where a xcex2 ratio=1, that is, the W/L ratio of an N type MOS transistor is equal to that of a P type MOS transistor is described hereinafter by way of example.
FIG. 8 is an input/output plot of a conventional CMOS inverter.
With an N type MOS transistor wherein a source voltage is 0V when an input voltage Vin is 0V, no conduction exists, and with a P type MOS transistor wherein a source voltage is 5V, conduction occurs because a gate-source voltage is xe2x88x925V. As a result, an output voltage becomes 5V.
With the N type MOS transistor, conduction starts at a point A where a threshold voltage 0.8V of the N type MOS transistor is exceeded while an input voltage is increased from 0V to 5V (VDD). An output voltage Vout is fully 5V up until then, and there is no direct passing of current between power sources. For a period from the point A to a point B in FIG. 8, the N type MOS transistor operates in the saturation region while the P type MOS transistor operates in the unsaturated region. For a period from the point B to a point D, both the N type MOS transistor and the P type MOS transistor operate in the saturation region, and in this period, the output voltage Vout varies most sharply, and an amplification degree of a small signal is at the maximum. Further, for a period from the point D to a point E between the points A and E, when direct current flows between the power sources, the N type MOS transistor operates in the unsaturated region while the P type MOS transistor operates in the saturation region. Upon the input voltage Vin increasing beyond the point E, a gate-source voltage of the P type MOS transistor becomes greater than xe2x88x920.8V, and no conduction occurs to the P type MOS transistor, so that there will be no passing of current between the power sources, and the output voltage Vout turns fully 0V.
Now, a point C is a point where Vin becomes equal to Vout, and is called a logic inversion voltage or a logic threshold voltage. Hereinafter, the term xe2x80x9clogic threshold voltagexe2x80x9d is in use.
According to the industry specification, when a power source voltage VDD is 1.8V, and a ground is at 0V, a range of 0 to 0.63V is designated as a low level while a range of 1.17 to 1.8V is designated as a high level. A range up to 0xcx9c0.63V signifies an allowance from 0V, and a range up to 1.17xcx9c1.8V signifies an allowance from the power source voltage 1.8V.
It is required as a characteristic of an inverter that both the allowances are to be secured with an adequate margin, respectively. In order to enable both the allowances to be secured with an adequate margin, respectively, even if there occur process variation and so forth, described as a problem with a conventional example, the characteristic of the inverter requires that a circuitry is set such that a range of variation of the logic threshold voltage at the point C is reduced.
An attempt has been made in the past to extend a range of conditions wherein a transition in condition does not occur, that is, a range of stable conditions wherein no current flows, by reducing an input voltage range wherein current flows. As a result, if there occur the process variation and so forth as described in the foregoing, the logic threshold voltage at the point C undergoes a large variation, and consequently, it becomes impossible to secure both the allowances adequately, so that an output against an input pulse at the low level and the high level, respectively, can not be adequately provided.
With a circuitry of such a characteristic as described above, at the time when the process variation, more specifically, variation in the threshold voltage of transistors, variation in process steps, change in temperature, variation in AC voltage, and so forth, becomes greater, resultant variation of the threshold voltage for determining the high level or low level becomes greater, so that there will occur a decrease in an allowance of a high level voltage or a low level voltage, capable of transmitting an input signal, from either the power source voltage or the ground level voltage.
Taking into consideration the process variation, voltage variation, temperature variation, and measurement error of a measuring instrument, there has existed a problem that a constant voltage interface is unable to meet the minimum voltage for an input at the high level and the maximum voltage for an input at the low level, in accordance with the industry""s standard specification.
In view of the problem described above, the invention may provide an input buffer circuit wherein even at the time when process variation becomes greater, resultant variation of a threshold voltage for determining the high level or low level is prevented from becoming greater.
An input buffer circuit of the present invention includes front stage circuits and a succeeding stage circuit. Each of the front stage circuits has a logic threshold voltage different from each other. The succeeding stage circuit has a P type MOS transistor and an N type MOS transistor connected in series. The succeeding circuit includes inputs connected to the front stage circuit. A logic threshold voltage of the succeeding stage circuit is set to be between the respective logic threshold voltages of the front stage circuits.